Conventionally, a NAND type flash memory is known as an example of a nonvolatile semiconductor memory device. A memory cell array in a NAND type flash memory is configured as an arrangement of a plurality of NAND cell units, each of the NAND cell units having a plurality of memory cells connected in series therein.
In such a NAND type flash memory, along with reduction in array pitch of the NAND cell unit, there is a need to reduce also wiring pitch of bit lines. However, because processing is difficult, a withstand voltage thereof deteriorates, an RC delay due to an increase in wiring resistance and wiring capacitance increases, and for the other reasons, it is difficult to conform reduction in wiring pitch of the bit lines with reduction in array pitch of the NAND cell unit.
Therefore, a system where two NAND cell units aligned in a word line direction share one bit line (shared bit line system) is also known. However, in this shared bit line system, a plurality of select transistors must be provided at one end of the NAND cell unit, which has been a barrier to improvement of bit density in the memory cell array.